2.1 Field of the Invention
The exemplary, illustrative, technology herein relates to systems and methods for growing device quality Gallium Nitride (GaN) thin film layers onto a silicon substrate.
The technology herein has applications in the areas of solid state power devices such as switches; rectifiers and other power devices as well as electro-optical devices such as lasers and light emitting diodes (LED's) whether fabricated as a stand-alone device or incorporated into a solid state integrated circuit device.
2.2 The Related Art
Conventional solid state power electronics is dominated by silicon (Si) devices in part because silicon device fabrication is a very mature and inexpensive technology with widely available design and manufacturing resources. Conventional solid state devices comprise a substantially single crystal silicon substrate layer and a silicon device layer or layers formed onto the substrate using a high temperature epitaxial deposition processes such chemical or gas deposition. An important requirement of the device layer or layers used in electronic and electro-optic devices is that the device layer also be formed as a substantially single crystal layer to achieve the desired electrical and optical properties. While some polycrystalline device layers are usable, substantially single crystal device layers are desirable for improved performance.
Several factors largely influence the crystal structure of the device layer. The first is how the crystal lattice structure or lattice spacing of the substrate layer compares with the crystal lattice structure or lattice spacing of the device layer. The second is how the coefficient of thermal expansion (CTE) of the substrate layer compares with the CTE of the device layer. The third is the deposition or reaction temperature of the deposition process used to deposit the device layer onto the substrate layer.
2.3 Crystal Lattice Mismatch
When the crystal lattice structure or lattice spacing is largely mismatched, e.g. between dissimilar materials, the crystal lattice spacing of the device layer attempts to match the lattice spacing of the substrate near the interface and this action generally disorganizes the formation of the natural lattice spacing of the device layer to the point that the device layer formed is substantially amorphous or polycrystalline or that dislocations in the device layer crystal lattice disrupt single crystal growth causing a flawed single crystal structure or a polycrystalline structure. In practice flaws in the single crystal structure potentially leading to cracking in the device layer especially when the device layer is stressed by a rapid thermal cycling. The conventional solution to this problem has been to grow silicon devices on silicon substrates which encourages single crystal growth and avoids the potential crystal lattice disruption at the interface. However silicon devices have failed to provide the desired electrical properties in many applications, especially in power devices such as power switches and rectifiers and further in optical devices that benefit from higher band gap materials such a Gallium Nitride (GaN).
In particular, silicon has significant limitations in power applications particularly with respect to excessive Joule heating which consumes operating power and is largely the reason why electronic systems require cooling, which further consumes operating power. This is especially problematic in battery powered systems where battery powered operating time is significantly reduced by Joule heating and system cooling used to alleviate the Joule heating. Another silicon based device limitation in power devices is its relatively low blocking voltage which limits the use of many silicon devices to low voltage applications, (e.g. <200 volts). A further silicon based device limitation is its relatively low bandwidth which limits switching speed in high speed devices such as switching power supplies of DC-DC power converters and limits its optical properties for use in visible wavelength emitters.
In spite of these limitations silicon based solid-state electronic devices are ubiquitously employed in the power control and distribution systems of most computers, automobiles, communications, consumer electronics, robotics, motor drives, electric power transmission and electric power generation systems. While this is largely due to the fact that silicon based solid state power systems are readily available and inexpensive there is a need in the art to develop more efficient, higher powered and faster switching power devices which in many cases exceed the practical limitations of conventional silicon power devices.
Device designers have long ago recognized that wide bandgap (WBG) semiconductor materials i.e. having a wider bandgap than silicon have more favorable properties for solid state power devices and electro-optical devices. In particular TABLE 1 compares the band gap and electrical properties of silicon vs wider bandgap semiconductors including silicon carbide (SiC) and gallium nitride (GaN) and diamond. As shown, all the WBG semiconductors provide an order of magnitude increase in critical electric field value (V/cm), which directly increases the blocking voltage of the power devices. Similarly all the WBG semiconductors provide at least a 4× increase in maximum operating temperature (° C.) which reduces Joule heating and potentially eliminates the need for cooling in many applications. In particular there is a need in the art to develop WBG device layers to address certain power and optical device needs not easily met by silicon devices and especially to develop GaN device layers.
One solution to using WBG semiconductor devices has been to change the substrate material to one that more closely matches the crystal lattice structure of the device layer. In one example solution that is commercially available GaN devices are grown onto Silicon Carbide (SiC) substrates specifically to reduce crystal lattice spacing mismatch as compare to GaN grown onto a silicon substrate. This is demonstrated by FIG. 1a which plots lattice spacing mismatch (in Å) vs. growth order of Sapphire (Al2O3), Silicon (Si), Silicon Carbide (SiC), Aluminum Nitride (AlN) and Gallium Nitride (GaN). As shown in FIG. 1a the lattice spacing of GaN is most closely matched to AlN (120a) followed by SiC, Si (130a) and finally Al2O3.
In another example solution that is commercially available GaN devices are grown onto Sapphire substrates to reduce thermal stresses induced into the substrate and device layer as a result of rapid and often non-homogeneous heating and cooling during the deposition process (discussed below). In particular the sapphire substrate more closely matches the coefficient of thermal expansion of the GaN device layer as compared to a silicon substrate and therefore the combination of GaN grown on Sapphire is less susceptible to thermal stresses that lead to wafer bow, cracking and generally degraded performance in the device layer. As shown in FIG. 1b the coefficient of thermal expansion (CTE) of GaN is more closely matched to the CTE of Sapphire than is to Si. In particular the CTE of GaN is most closely matched to SiC and AlN followed by sapphire and then silicon.
However in both of these solutions the need for a non-silicon substrate layer requires specialized processing equipment to grow and process non-silicon substrates substantially increasing end user device cost and virtually eliminates integration of GaN devices into silicon based integrated circuits except as an added stand-alone component. While these conventional solutions meet a niche demand for GaN devices where a silicon device is inadequate; they come at a high cost and in limited configurations mainly due to their inability to be manufactured using convention silicon based processes. Accordingly there is still a need to form device quality (i.e. substantially single crystal growth) GaN device layers onto silicon substrates.
It is known that high temperature deposition processes increasingly favor the formation of single crystal films. For example, Strike et al. in GaN, AlN and InN: a Review (J. Vac. Sci. Technology B 10(4), July/August 1992) discuss how heteroepitaxial growth of device layers of the III-V nitrides occurs on a sapphire substrate when GaN films are applied by a metal-organic chemical vapor deposition (MOCVD) process with reaction temperatures between 900 and 1000° C. However Strike et al. specifically points out that the sapphire substrate is used for its stability at high temperature (1000° C.) required for epitaxial growth in various CVD techniques, even though sapphire has a less than desirable crystal lattice spacing mismatch and a less than desirable CTE as compared to GaN.
While it is widely accepted that the high reaction temperature of the MOCVD process favors heteroepitaxial growth that exhibits single crystal film behavior e.g. as determined by X-ray diffraction analysis, the high reaction temperature has other drawbacks associated with stresses induced into the substrate and the device layer as a result of rapid and often non-homogeneous heating and cooling during the deposition process as well as the incorporation of unwanted materials into the substrate, e.g. caused by diffusion of the device layer material into the substrate.
In a conventional MOCVD reactor, stress management is a primary concern and limits the quality of the deposition. In particular wafer bow resulting from thermal cycling is a primary concern in MOCVD process equipment and is preferably limited to less than 100 μm in order for the wafer to be further processed on conventional wafer handling and processing tools for high volume manufacturing. While this problem has been addressed by forming “stress compensation layers” in MOCVD films these stress compensation layers degrade the device layer performance and add cost.
Recently attempts have been made to grow device quality GaN onto a Si substrate by metal-organic chemical vapor deposition (MOCVD). However when the GaN is grown directly onto the silicon substrate there is undesirable cracking due to the large crystal lattice spacing mismatch (16.9%) between the GaN and the silicon and the large coefficient of thermal expansion (CTE) mismatch between GaN (αa 5.59×10−6 K−1) and Si(αa 3.77×10−6K−1). In particular Pan et al. (Growth of GaN film on Si(111) Substrate using a AlN sandwich structure as buffer Joun. Of Crystal Growth 318 (2011) 464-467) report that the GaN epitaxial layers grown uniformly on Si substrates suffer from randomly distributed cracks, which are mostly caused by the CTE mismatch.
Pan et al. offer several solutions including first growing a buffer layer of high temperature H-T Aluminum Nitride (AlN) onto the silicon substrate by MOCVD, which performs two functions: a) to reduce crystal lattice spacing mismatch; and, b) to provide a nucleation layer for the GaN layer. In addition Pan et al. suggest several other example structures combining the H-T nucleation layer e.g. AlN over laid with a combination of layers in the Al—Ga—N ternary system. The problem is that the nucleation layer is polycrystalline due to the crystal lattice spacing mismatch between AlN and Si, and the spacing mismatch causes the grain boundaries between the nucleation layer and the GaN layer to produce a high density of dislocations or domain mismatches in the epitaxial GaN layer. While Pan et al. report that cracking in the GaN layer is reduced by the application of the high temperature H-T AlN buffer or nucleation layer which provides less lattice spacing mismatch with the GaN layer as compared to the lattice spacing mismatch of GaN with the silicon substrate: this solution fails to address the problems associated with high reaction temperature of the MOCVD process which still leads to wafer bow, which increases with increased device layer thickness. Accordingly no solution is currently provided to overcome the need for high temperature epitaxial growth provided by MOCVD and other high temperature deposition techniques while avoiding the problems associated with the resulting wafer bow and cracking typical of high reaction temperature processes.
Finally, there is a further important limitation imposed by the approach of growing GaN on a dissimilar substrate with a nucleation layer. In particular, the key role of the nucleation layer in promoting the epitaxial growth precludes the option of having device layers at the bottom of the GaN film for vertical device architectures. Unfortunately this limitation is devastating for designing high-power devices, where the vertical architectures often have significant performance advantages in carrying high current loads and blocking high voltage. In particular vertical architectures take advantage of an increased device layer thickness (e.g. 3 μm or more) to increase the breakdown voltage of the device (e.g. to 1000 Volts or more). However in order to take advantage of the increased layer thickness terminals are required on opposing faces of the device layer which means that both the substrate and the nucleation layer needs to be removed to gain access to both faces of the device layer. Accordingly no solution is currently provided to overcome the need for building vertical devices when the device layer includes a nucleation layer applied between the substrate and the device layer.
There are three independent areas where the growth of high quality films is important. The first is in the growth of the bulk film (e.g. multiple microns of film on top of the substrate) such as for vertical devices. The second is in the growth of the gate structure (on top of the oxide), and the third (for planar devices) is in the region between the gate and the drain to passivate the surface. In this third region, surface states (traps) on planar high-electron-mobility-transistor (HEMT) devices lead to current collapse in the device and the deposition of high quality GaN films in this region improves device performance. All three of these applications require the fabrication of high quality (low defect) GaN films which is are not adequately addressed in the art.
TABLE 1Important material properties of Si and various WBG materials for high-powerelectronic applicationsPropertySi3C-SiC6H-SiC4H-SiCGaNDiamondBandgap (eV)1.122.32.93.23.395.6Electron Mobility1450100041595010004000(cm2/V-s)Hole Mobility (cm2/V-s)4504590115353800Critical Electric Field3 × 105  2 × 1062.5 × 106 3 × 1065 × 106107(V/cm)Saturation Velocity1072.5 × 107   2 × 1072 × 1072 × 1073 × 107(cm/s)Thermal Conductivity1.35551.320(W/cm-K)Maximum Operating125500500500650700Temperature (° C.)Dielectric Constant11.79.69.7108.95.7
2.4 Definitions
The following definitions are used throughout, unless specifically indicated otherwise:
TERMDEFINITIONhomoepitaxialThe growth of a crystalline film on a crystallinegrowthsubstrate wherein the film and the substrate are thesame material and the crystal orientation of thecrystalline film mimics the crystalline orientation ofthe substrateheteroepitaxialThe growth of a crystalline film on a crystallinegrowthsubstrate wherein the film and the substrate aredifferent materials and the crystal orientation of thecrystalline film mimics the crystalline orientation ofthe substratedomain matchingEpitaxial growth of thin films where integral multiplesepitaxyof major crystal lattice planes match across theinterface.